The present invention relates to a semiconductor design technology, and more particularly, to a termination circuit.
Recent research trend is to develop a semiconductor memory device, including Double Data Rate Synchronous DRAM DDR SDRAM with a large storage capacity. Hence, the number of memory cells for storing data has been greatly increased. The increase in the number of the memory cells may also lead to an increase in chip size, and also to an increase in the number of lines conveying signals inside the semiconductor memory device. For example, a semiconductor memory device of 512 MB may include four memory banks, each of which includes a plurality of memory cells, and a semiconductor memory device of 1 GB may include eight memory banks. In other words, the increase in the memory banks is also accompanied by a larger and longer number of data lines carrying data and larger load on the data lines.
Meanwhile, data lines provided in a semiconductor memory device are classified into a segment input/output line, a local input/output line, and a Global Input/Output GIO line depending on positions where they are. Among these lines, the GIO line may cause data distortion and loss because it has a relatively larger loading than that of the segment input/output line or the local input/output line.
To resolve this problem, a repeater system is typically used to reduce data distortion by inserting two stages of inverters approximately in the middle of the GIO line. However, this repeater system is nothing but an enhanced driver in its structure, and thus results in large current consumption since the number of transistors used therein and the size of driver are large. In order to mitigate the deficiency, a termination system for GIO line has been proposed.
Hereinafter, a termination system will be briefly described. According to a typical termination system, a GIG line is pre-charged to a termination voltage level, e.g., a ½ voltage level of an external power supply voltage prior to loading data on the GIO line and, even during a period when data is applied, this termination operation is continuously performed, thereby reducing a variation in voltage level of data transferred onto the GIO line, that is, a swing width of data. As a result, since the data being transferred through the GIO line has a small swing width, current consumption caused by data transfer can be reduced and data can be transferred more quickly.
FIG. 1 is a circuit diagram illustrating a termination operation of a conventional semiconductor memory device.
As shown, the conventional memory device includes a termination driver 110 and a latch unit 130.
The termination driver 110 drives a GIO line with a termination level in response to a termination enable signal EN_TERM, and the latch unit 130 latches data being applied to the GIO line in response to the termination enable signal EN_TERM.
Here, the termination enable signal EN_TERM is activated during a read operation of the semiconductor memory device and inactivated during a write operation thereof. That is, during the read operation, the termination driver 110 performs a termination operation on the GIO line, while the latch unit 130 latches data applied to the GIO line during the write operation.
The following is a detailed description about a termination operation of a termination circuit.
When a termination operation of the termination driver 110 is to be performed during a read operation, the GIO line is pre-charged to a termination level and data being applied thereto is transferred with a swing width caused by a termination operation. Herein, since a current accompanying the data transferred to the GIO line may be opposed by a drive current being transferred from the termination driver 110 to the GIO line, the data may not have a full swing width but has a small swing width.
Subsequently, the termination operation of the termination driver 110 is disabled during a write operation, and the latch unit 130 is enabled to latch the data being applied to the GIO line.
In general, the termination circuit has to properly control a drive current in its termination operation, and thus, its design needs to be made carefully. If the drive current is excessively large, a transfer speed of data being transferred to the GIO line may be faster but data loss and current consumption may be larger. On the other hand, if a drive current is excessively small, current consumption may be reduced but a transfer speed of data may be slower and coupling may occur between adjacent GIO lines.
Particularly, the transfer speed of data becomes a very critical factor in operation of a receiver (not shown) which is connected to the GIO line and receives data being transferred through the GIO line. The receiver should receive data at a specific time because the margin between the received data and the specific time depending on the transfer speed of data may be different. Consequently, if the transfer speed of data is excessively faster or slower than a target speed, a margin failure in the operation may occur.
Meanwhile, the semiconductor memory device performs diverse operations by using an external power supply voltage and a ground voltage applied thereto. Here, the external power supply voltage may have a different level depending on products. Similarly, the termination circuit also carries out a termination operation by utilizing the external power supply voltage and the ground voltage inputted thereto. As noted above, the external power supply voltage applied to the termination circuit may depend on products. Consequently, the drive current used for the termination operation may vary corresponding to the external power supply voltage, and thus the transfer speed of data may also vary. As described above, this causes margin failure when the data being transferred through the GIO line is received by the receiver.